Various forms of memories have been proposed for providing video processing functions. As explained below, the known memories vary substantially in complexity depending upon the specific application in which they are used.
At one end of the range of complexity there are simple shift registers, charge-coupled devices and glass delay lines for providing a fixed amount of delay. Such devices are useful, for example, in line comb filtering applications for the separation of luminance and chrominance signals. They are also useful, as another example, in progressive scan processing systems for providing vertical interpolation or "line averaging" to generate extra lines of video for display. Also, in progressive scan applications, a one-line shift register may be "read" or "clocked" at twice its input rate to thereby provide the function of time compression of video lines. Such devices, however, have limited addressing capabilities.
In applications where substantial delay may be desired, one may combine a number of serial and parallel shift registers as described, for example, by P. K. Weimer in U.S. Pat. No. 3,763,480 entitled DIGITAL AND ANALOG DATA HANDLING DEVICES which issued Oct. 2, 1973. In an embodiment of the Weimer memory, serial input signals are converted to parallel form by a serial-in parallel-out (SIPO) shift register. Once in parallel form, the data is successively delayed by a plurality of parallel registers and the output of the last parallel register is coupled to a parallel-in serial-out (PISO) shift register for conversion of the data back to serial form. This structure, however, is not adapted for applications requiring concurrent reading and writing at difference clock rates.
Dual port video memories are known which feature full addressing capabilities in which any pixel (picture element) in any location can be written (stored) or read (recovered). In a conventional video RAM of this type, the operations or reading and writing can take place concurrently. Such devices are particularly useful in video graphics processing in computers and in "picture in picture" processing in television receivers. An example of a dual ported video RAM is the type MCM68HC34 device manufactured by Motorola and described, for example, at pages 3-10 in chapter 5 of the Motorola data book "Memories" that was published (second printing) in 1988. A problem with such devices, however, is that the read/write addressing requires many address lines and complex decoders to address cells in the random access memory (RAM) and addresses must be supplied in binary form requiring a number of write address bit inputs and a number of read address bit inputs.
The addressing problem can be reduced, to a certain extent, by transmitting the binary address data serially to the memory as described, for example, in U.S. Pat. No. 4,821,226 of Christopher et al. entitled DUAL PORT VIDEO MEMORY SYSTEM HAVING A BIT-SERIAL ADDRESS INPUT PORT which issued Apr. 11, 1989. In an embodiment of the Christopher et al. memory system, read and write address data and a control signal are serially loaded into a shift register. Address sequencing circuitry transfers the read and write address values to integral read and write address registers and, based on the control value and initiates respective read and/or write operations. Although addressing is some-what simplified in such systems, the addressing is still essentially in binary code and relatively complex address decoders and storage registers are required.